ELEC211讲解、web/HTML编程语言辅导、讲解web设计

日期：2020-05-05 10:56

Exp 28 Part II, Ver. 7, Apr 2020
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Experiment 28 - Digital Electronics with Altera
Part II: The Practical Part
Department of Electrical Engineering & Electronics
April 2020, Ver. 7
Experiment Specifications
Module(s) ELEC211
Experiment code 28
Semester 2
Level 2
Lab location Home PC or laptop. Ideally Windows – see specific
instructions for MAC OSX.
Work Individual.
Timetabled time Originally 7 hours, 1 lab day. Allocate 2-3 times this long to
complete your practical work individually, and then further
time to write your report. Advice: take screenshots so you
can write the report as you go.
Subject(s) of
relevance
Digital Logic Design, FPGAs and VHDL
Assessment method Online submission via VITAL using the provided MS Word
submission template. See the instructions section.
Submission deadline Thursday 7th May 2020, 23:59 local time (BST), submitted
online via VITAL.
Important: Marking of all coursework is anonymous. Do not include your
name, student ID number, group number, email or any other personal
information in your report or in the name of the file submitted via VITAL.
A penalty will be applied to submissions that do not meet this requirement.
Exp 28 Part II, Ver. 7, Apr 2020
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Instructions:
? Read this script carefully before attempting the experiment.
? It is also strongly recommended that before starting, you catch up on the
Stream Capture for all lectures so far on VITAL, especially Lectures 22 and 23.
? The Pre-Lab Questions should be answered before attempting this experiment. They
are available on VITAL (online) and worth 30%. Other material is there to guide you.
? To submit your practical work in this experiment, download the file “Exp 28-
Submission Template” from “Lab Scripts” folder. Fill in the gaps with the required
information and upload to VITAL.
? Important: Marking of all coursework is anonymous. Do not include your name,
student ID number, group number, email or any other personal information in your
report or in the name of the file submitted via VITAL. A penalty will be applied to
submissions that do not meet this requirement.
? Results should be submitted as screenshots. Make sure they are all clear and
readable. Marks will not be given if the screenshots are unclear.
? Keep a copy of all the required information, results, screenshots, etc. after carrying
out the experiment to use for your submission on VITAL.
? Refer to the document “Exp 28 - Supporting Material” on “Lab Scripts” folder which is
available on VITAL for further details and information.
? Marking scheme highlights (see Submission template for details):
1. The pre-lab test [30 Marks]
2. The compilation result of the design in Section 2.3 [3 Marks]
3. The output simulation waveform in Section 2.4 [3 Marks]
4. The schematic YI_7SegmentDecoder.bdf of Section 2.5 [4 Marks]
5. The simulation waveform of Section 2.6 [4 Marks]
6. The schematic YI_dec_counter.bdf of Section 3.1 [4 Marks]
7. The simulation waveforms of Section 3.1 [4 Marks]
8. The schematics of Section 3.2 with pin assignment [4 Marks]
9. The simulation waveforms and explanations of Section 3.2 [4 Marks]
10. The schematics and simulations of the divide-by-12, and of the
cascading of two divide-by-12 counters, of Section 3.2 [10 Marks]
11. The code and simulation of Section 4.1 [10 Marks]
12. The code, schematic design and simulations of Section 4.2 [10 Marks]
13. The code, schematic design and simulations of Section 4.3 [10 Marks]
? Important: When taking snapshots from the screen (for schematic or simulation), for
each and every snapshot please FIRST use PrintScreen under MS Windows, or
CMD+SHIFT+3 or Screenshot under macOS (which shows the entire desktop
including time and date and helps to identify this as uniquely your work) AND THEN
ALSO use the Snipping tool (MS Windows) or Screenshot tool (macOS) to show
only the relevant part of your design or simulation. If the entire desktop is not visible
in your first screenshot, the associated ‘focussed’ screenshot will be ignored and the
corresponding section of your report will receive a mark of zero.
? Throughout this assignment, please insert your initials and underscore, at the
beginning of all saved filenames. This should be readable from the title of the
relevant window. This instruction is implied below with “YI” for “your initials”.
If this format is not followed, corresponding sections will receive a mark of zero.
? Including screenshots of other people’s work is considered as academic malpractice
and will be penalised in accordance with the University Codes of Practice.
? All code should be included as text and not screenshots.
Exp 28 Part II, Ver. 7, Apr 2020
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Before you begin!
To attempt this experiment you will need to download and install Quartus II 13.0sp1
Web Edition on your machine.
Preparing for download / installation
Students running mac OS / Mac OSX
Quartus II is software that runs under Microsoft Windows OS. If you run a macOS /
Mac OS X, you will need to first install a Microsoft Windows OS emulator called
CrossOver. This emulator is provided by the CodeWeavers company, a trial version
lasting 14 days is available and it can be downloaded from:
https://www.codeweavers.com/products/crossover-mac/download .
For downloading CrossOver, you are required to insert your name and email
address. This will enable the “Download Trial Now” button. After completing the form
and clicking on the button, the browser should automatically ask you to download the
“crossover-19.0.1.zip” file. Save the zip file to a location of your choice, then extract it
and copy the “CrossOver” program into the “Applications” folder. Launch CrossOver,
an alert message should open as shown in Figure B1. Make sure that CrossOver
was downloaded from “www.codeweavers.com”.
Figure B1. macOS security feature notifying the user that CrossOver has been downloaded from the Internet
Click “Open” to continue and another message should open to give you the option to
launch CrossOver in different versions (Figure B2); click “Try now” to run the trial
version. This will launch CrossOver in trial mode and another dialog window should
open asking you if the CodeWeavers company can log statistics about the usage of
the application, click on the corresponding button depending on your personal
preference. You now have CrossOver correctly installed and ready for use.
Figure B2. CrossOver trial
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All students (including those running mac OS / Mac OSX)
Visit https://fpgasoftware.intel.com/13.0sp1/?edition=web&platform=windows and
ensure that the selection at the top of the screen is as shown in Figure B3. (If you
are running Linux, please change your selection accordingly.)
Figure B3. Correct selection for Quartus II Web Edition download, for those using a Windows PC or emulating
Windows via CrossOver on a MAC.
Ensure that “Individual Files” is selected as shown in Figure B4, and click to
download the highlighted files but see next section before proceeding further.
Note: MAC users: in CrossOver, you may find that the files will only install on a Win7
bottle within the emulator – this is OK.
Figure B4. Minimum files for a functioning download of Quartus II Web Edition.
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Download/installation of Quartus II including Cyclone device support
Important – account creation
When you try to download the two files, Intel will prompt you to create a free account.
The next part can be confusing so be sure to follow the steps carefully to avoid
downloading a trial subscription edition!
1. Follow the process to create an account (two pages of questions)
2. Do not try to return to the previous page in the browser via the ‘back’ button;
this would auto-redirect you to a premium version of the software. Instead,
close your browser and click the above link again to return to the free
Web edition download page.
3. When you click again to download the above files, you will be required to sign
in AGAIN. Sign in, and this time it should lead to a download of the free Web
edition of Quartus II, and of Cyclone. Please be aware that these installation
files together total 2.1 GB and depending on your internet connection speed,
could take anything up to a few hours to download. Please be patient.
Installing Quartus II Web Edition
Now, install the software by opening the first file (QuartusSetupWeb-13.0.1.232 or
similar) and following the instructions. [Note that the fully installed program, with
device support, will take around 5.9 GB of disk space which you should ensure is
available.] When installation of Quartus II is complete, you may be prompted to
‘install device support’ or a similar message, if this has not been automatically done.
This leads in to installation of the Cyclone device support.
Continuing to install Cyclone device support (if not auto-installed)
Take the above option and follow the wizard. For example, on a Windows 10 PC you
will see a dialogue box which asks if your .qdz files (for the Cyclone) are to be found
in C:\altera\13.0sp1\quartus\bin. Whichever location is listed, cut and paste the
.qdz file to that location. Then, continue to follow the instructions in the wizard.
HOWEVER, if at some point the options are greyed out and you see an error
message, this means that the Cyclone device support has already been installed.
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1. Introduction
This experiment will take you through a tutorial on how to use the Altera Quartus II FPGA
(Field Programmable Gate Array) development package and an awareness of the DE1
development board (Figure 1).
Figure 1. Altera DE1 Board
It is important to know the overall structure of this experiment before starting it. There are
supporting documents available in Vital to familiarise you with each stage. Make sure you
read them before you begin your work, and that you are also up-to-date with the ELEC211
stream captures on VITAL as mentioned above. Three steps are required in total for any
project you design. It is important to compile it first to see whether there is/are any error(s)
(“compile” part). After your compilation, you need to simulate the project based on some
known input, to check its output is correct (“simulation” part). Finally, in ordinary
circumstances you could test your project on the DE1 board (“test on DE1” part). This
experiment is built around these three steps, guiding you to a correct design such that Step
2 (simulation) works correctly and would, to the best of your knowledge, give a correct output
on the DE1 board.
2. Schematic Capture [14 Marks]
Schematic capture is one of the most common methods for entering a design. It involves
using a design tool to draw a schematic of the desired circuit. This is probably the easiest
method of design capture to understand, but it is not necessarily the most efficient. The
Quartus II software includes schematic symbols and models for the most common 74-series
TTL IC's. This means that a designer can easily take a schematic or existing design of a
circuit implemented using TTL parts and enter that schematic into the software. The entire
circuit, which may contain dozens of TTL chips on a printed circuit board, can then be
compiled into a single FPGA package. Although very good for updating old projects,
schematic capture is not usually the most efficient way of capturing the behaviour of new
Exp 28 Part II, Ver. 7, Apr 2020
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designs. For that purpose, a Hardware Description Language (HDL) is probably the more
efficient. We will cover a HDL called AHDL (Altera HDL) in a later section of this experiment.
2.1. Start the Altera software
Select Start -> All Programs -> Altera 13.0.1.232 -> Quartus II 13.0sp1 (32-bit or 64-bit
depending on your appropriate download). The Quartus II Manager window will open
(Figure 2). This window allows you to access all of the different tools that you will be using
from one place. (If the “Getting Started with Quartus II” window appears close it by clicking
the “x” at the top right).
Figure 2. Quartus II Manager Window
The tool bar along the top is basically the same for all applications. Some icons will be
greyed out, depending on which windows are in the foreground. Some applications will have
their own tool bars, but these will be along the left side of the window.
Select File->New... Select Block Diagram/Schematic File (Figure 3). Click OK.
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Figure 3. New item selection window
The Schematic Editor window will open. Select File->Save As. Select your ‘M’ drive in the
‘Drives:’ dialog. Create a folder with the name “Exp28”, and under that folder create another
folder and name it dec7448. Select the “dec7448” subdirectory in the “Directories:” dialog
and enter YI_dec7448.bdf in the File Name field, where YI stands for your initials. E.g.
Joseph Bloggs would enter JB_dec7448.bdf. In the Save as type field choose
BlockDiagram/Schematic Files (*.bdf). Click Save (Figure 4).
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Figure 4. Save As Dialog
Click Yes to creating a new project in the New Project Dialog (Figure 5).
Figure 5. New Project Dialog
This will start the New Project Wizard (Figure 6).
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Figure 6. New Project Wizard
Click Next to move to page 1 of the New Project Wizard (Figure 7). The working directory
and name of the project should have been entered automatically. Click Next to move to
page 2 (Figure 8).
Figure 7. New Project Wizard - page 1 Figure 8. New Project Wizard - page 2
Click Next to move to page 3 of the New Project Wizard (Figure 9). Select Cyclone II family
with the correct package (FBGA), pin count (484), and speed grade (7). Select the
EP2C20F484C7 device and click Next to page 4 of the New Project Wizard (Figure 10).
Exp 28 Part II, Ver. 7, Apr 2020
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Figure 9. New Project Wizard - page 3 Figure 10. New Project Wizard - page 4
Click Next to move to page 5 of the New Project Wizard (Figure 11). Click Finish to exit the
New Project Wizard.
Figure 11. New Project Wizard - page 5
2.2. Using the Graphics Editor
Double click anywhere in the empty Graphic Editor window. The Symbol dialog box will open
(Figure 12). Expand others\ maxplus2 library and then select 7448 in the Libraries box
and click OK.
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Figure 12. Symbol Dialog box
Figure 13. 7448 Symbol Selection
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A 7448 symbol will appear in the Graphics editor screen (Figure 14). Place the 7448 symbol
by left clicking.
Figure 14. Graphics Editor
The Graphics Editor has many built in symbols. It has primitives such as AND gates, NOR,
gates, etc. It also has megafunctions, which are combinations of gates that form higher level
objects such as multipliers and dividers. Double click on any empty part of the Graphics
Editor window to bring up the Symbol dialog box again. In the Symbol Libraries window
expand the Primitives folder to see the different symbols available in the primitives library.
Don't select any right now; you can look at the symbols in more detail later, if you want to.
For now, just click on Cancel and continue with the tutorial.
Since we just want to emulate a 7448, most of our work has already been done. All we need
to do is make input and output connections and connect any control lines that need to be
set. To see what is inside the 7448, double-click on the 7448 symbol. You should see a
schematic like that shown in Figure 15.
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Figure 15. 7448 Schematic
Aren't you glad you didn't have to draw the whole thing? By double-clicking on the symbol,
we have gone down a level and are now looking at the inside of the symbol. This is an
example of what is meant by a design hierarchy. We have a top level schematic, which
contains the 7448 symbol. If we go down one level into the 7448, we can see the schematic
for the 7448 itself, which is made up of primitives such as logic gates and I/O pins. Close the
window showing the inside of the 7448 (it will have the title 7448.bdf) by clicking on the
orange cross.
Now we need to add inputs and outputs to the drawing. Double click inside the Graphic
Editor window, anywhere to the left of the 7448 symbol. You should get the Symbol dialog
box like before. Enter input for the symbol name to select an input (Figure 16).
Figure 16. Input Symbol
Click OK and place the input symbol in your design by moving it to the correct location and
left clicking (Figure 17). The input symbol represents an input to that layer of the design. If
the design is the top layer then it represents a physical input pin on the PLD.
Exp 28 Part II, Ver. 7, Apr 2020
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Figure 17. Design with one input
2.3. Drawing Your Schematic [3 Marks]
Now we need to connect the input pin of the PLD to one of the inputs of the 7448. Move the
cursor to the right end of the horizontal line in the input pin symbol. The cursor will turn into a
cross, indicating that you can attach a wire to that point.
Now click on the right end of the input signal and hold the mouse button. Drag the cursor to
the left end of the pin labelled A on the 7448 and release the button. You have now
connected the PLD input pin to the input of the 7448. It should look something like Figure
18.
Click on the input pin symbol and drag it so that the wire between it and the pin on the 7448
is straight. The input pin should be selected. Select Edit->Copy to copy the pin. Click just
below the first pin to select an insertion point and then select Edit->Paste to paste in the
copy of the pin. (Alternatively, you can hold down the Ctrl key on the keyboard and click on
and drag the pin. A copy will be created wherever you dragged to). Move it until it is just
below the first pin and aligned with it horizontally. Connect the second pin to the B input.
Repeat this to create a third and fourth pin. Connect these to inputs C and D. Your
schematic should now look like Figure 19.
Figure 18. One input connected Figure 19. Four inputs connected
Although the pins on the 7448 are labelled correctly already, the design inputs are all
labelled PIN_NAME. Double click on the first pin and change the Pin Name to INPUT_A.
Depending on where you click the Pin Properties Dialog (Figure 20) may appear. This also
allows you to change the pin name.
Repeat this for the other three pins, naming them INPUT_B, INPUT_C, and INPUT_D, as
shown in Figure 21.
Figure 21. All input pins named
Now we need to add output pins. Repeat the procedure you used to get the first input pin,
except use the symbol name output. Copy the pin to get a total of seven pins. Connect them
to the seven outputs labelled OA through OG. Label the output pins as OUTPUT_A through
OUTPUT_G. Your schematic should now look like Figure 22.
Figure 22. All pins named
We have three input pins that are not connected. Connect them to positive power supply
voltage using the following procedure. Add a new symbol to the schematic above and to the
left of the 7448 symbol, using the same procedure you did for the input and output pins. This
symbol name should be vcc. This symbol represents the positive supply voltage connected
to the FPGA. Connect the vcc symbol to the LTN, RBIN, and BIN pins on the 7448. Your
schematic should like Figure 23. Note that when wires cross, they are NOT connected
unless there is a connection dot where the wires cross. So the Vcc symbol is NOT
connected to any of the input pins A, B, C, and D. The schematic is now complete. Select
File->Save to save your work.
Figure 23. All pins connected
Double click (or right click and select Properties) on the vcc and change its instance name
to inst1 (Figure 24).
Figure 24. Symbol Properties Dialog
Now compile the design, under the processing dialog click on start compilation, Figure 25.
Figure 25. Start compilation dialog
Finally, you should get a dialog box like the one in Figure 26, stating that the compilation
was successful.
Figure 26. Full Compilation Dialog
If you did everything correctly, you won't see any errors, but in developing actual projects,
you will probably see some errors and lots of warnings. An error is a problem so serious that
the compilation can't continue. You will have to fix the error before you can compile. A
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warning won't usually stop the compilation, but you need to look at the warning message to
see if it something you need to fix before proceeding. Some warnings can be ignored, while
others will need to be fixed. Look at the help messages and use your own judgment and
experience to determine which warnings you need to heed.
The error messages are generally fairly detailed and clear and you can usually determine
what they mean just by reading them. You can also use the Help->Message List to get
more information on the error.
The Compilation Report (Figure 26) shows how many pins your design used, and also how
many Logic Cells (LCs) your design used.
Figure 27. Compilation Report
2.4. Waveform Entry for Simulation [3 Marks]
We have entered our design and it has compiled without errors. The next step would likely
be to run the program and see if it worked as we expected.
Use the inputs similar to the waveform given in Figure 28 and find the output. (Use the
Supporting material document).
Figure 28. Completed Input Waveform
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2.5. Design Project (Decoder) based on AHDL Code [4 Marks]
Create a project and a schematic file named YI_7SegmentDecoder.bdf as outlined in
Section 2.1. The next thing will be to create an AHDL file and add it to the schematic. Select
the AHDL file type from the File->New menu item. Then enter the text code for the decoder
as shown in Figure 29. The lines beginning and ending with the % sign are comment fields
which are used to document designs. Hint: use of the help system might save a lot of typing
here. If you can find a relevant section on creating decoders, you should then be able to cut
and paste the text into your tdf file (Figure 30). If you have difficulty navigating the Quartus
II help pages, you can also find the relevant text in the Prelab material instead.
Figure 29. Decoder TDF file
Figure 30. Help file for decoders
Save the file using File->Save in your project’s directory with the filename
“YI_7SegmentDecoder.tdf” and make sure that the check box for Add file for current
project is selected (Figure 31).
M:/amin/_7SegmentDecoder/_7SegmentDecoder - _7SegmentDecoder
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Figure 31. Save As Dialog
To create a graphical symbol from this file to include in the schematic select File-
>Create/Update->Create Symbol Files For Current File.
Next we need to insert the created symbol into the top level schematic file. Right click
anywhere on the window of the top-level bdf file and select Insert->Symbol (Figure 32).
Expand the Project Library and select the 7Segment module. Select OK to place the symbol
in your design.
Figure 32. Select Symbol Dialog
Notice how the inputs to the 7segment module are shown as a single thick line and labelled
i[3..0]. This represents a “bus” of four connections. As we can’t directly connect single wires
to buses we need to label the bus and the inputs using common names. To do this, extend
the bus line from the 7segment module to the left by pressing the left mouse button and
dragging. Then right click on the line and select Properties. Enter the Bus Name (Figure
33).
_7SegmentDecoder
_7SegmentDecoder
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Figure 33. Bus Properties Dialog
Type in “in[3..0]” which indicates a group of four signals labelled in[3] down to in[0]. Then
insert input and output pins as you did for the first project but this time give the names of
in[3] … in[0] to the inputs (Figure 34).
Figure 34. Schematic with input and outputs
Finally you need to invert the polarity of the output signals by adding seven inverters to the
design. Click on the Symbol button (the AND gate –Figure 35) in the toolbar and type not in
the name drop-down list.
Figure 35. Symbol Tool Selection
Select “Repeat-insert mode” and then select OK (Figure 36).
Figure 36. NOT Symbol
Add seven instances of the NOT gate and connect them between the outputs of the decoder
and the output pins. Now the design is complete. Save it and compile it.
Next we want to assign the pin numbers (please refer to the document “Exp 28 - Supporting
Material” in the “Lab Scripts” folder available on VITAL). The result is shown in Figure 37.
Save the design, and finally, simulate the design (see below).
Figure 37. Design with pin allocations
Now, we’ll simulate this design.
2.6. Input Simulation for Decoder [4 Marks]
From File menu, click on the University Program VWF. Save the opened .vwf file in the
project’s folder with YI_7SegmentDecoder name (Figure 38).
Figure 38. Save Vector Waveform dialog
Open the Node Finder window by select Edit->Insert->Insert Node or Bus (Figure 39).
Figure 39. Insert Node or Bus Dialog
On the Node Finder Window click on the List button to list all the nodes. By clicking on the
>> button, copy all the signals to the Selected Nodes area (Figure 40).
M:\amin\_7SegmentDecoder
[_7SegmentDecoder.vwf]
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Figure 40. Selected Nodes
Click OK and then OK again to return to the Waveform editor (Figure 41).
Figure 41. Waveform Editor
Note that the inputs are grouped together with a default base of “Binary”. When using buses
it is often easier to only display the bus value in “Hexadecimal”. Right click on the in bus and
change its radix to Hexadecimal (Figure 42).
Figure 42. Change radix to Hexadecimal
[_7SegmentDecoder.vwf]*
[_7SegmentDecoder.vwf]
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Highlight the in bus by left clicking on its name, then click on the Count Value button.
Change the Count period to 50 ns and then click OK (Figure 43).
Figure 43. Count Value Dialog
This will generate a counting input (Figure 44).
Figure 44. Waveform showing count simulation
Save the file and close the Window. Select Simulation?Run Functional Simulation. (First,
however, just as in the Supporting material Section 4.2, select Options and check that
‘Quartus II Simulator’ is selected.) Notice that there is no delay between input and output in
the Functional Simulation (Figure 45). Also notice that for an input value of “0” only the G
LED is disabled (high) whilst all the other LEDs are on (low).
Figure 45. Functional Simulation Results
Ordinarily, you would next program the FPGA by selecting the Programmer from the Tools
menu. Once the device had been programmed, you would be able to observe the LED
outputs for the 16 combinations of DIP switch inputs.
[_7SegmentDecoder.vwf]*
[_7SegmentDecoder.sim.vwf] (Read-Only)
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3. Counter design in AHDL [26 Marks]
3.1. Counter design in AHDL [8 Marks]
Perhaps the simplest sequential system to implement is a simple counter.
SUBDESIGN dec_count
(
enc, ent, clk : INPUT; % two enables and the clock %
clear : INPUT; % Synchronous clear %
value[3..0] : OUTPUT; % Four output bits %
rco : OUTPUT; % ripple carry out %
)
VARIABLE
count[3..0] : DFF; % locally define 4 D-Flip-Flops for the count %
BEGIN
count[].clk = clk; % Connect the clock input to the DFF’s clock %
value[] = count[]; % connect the outputs of the DFFs to the outputs %
IF (clear) THEN % if clear is true clear the count i.e. %
count[].d = 0; % load the flipflops with zero %
ELSIF (enc & ent & (count[].q != 9)) THEN
% if both enables are true and the count does not %
count[].d = count[].q + 1; % equal nine then add one to the count value %
ELSIF (enc & ent & (count[].q == 9)) THEN
% if both enables are true and the count does %
count[].d = 0; % equal nine then load the flip flops with zero %
ELSE % with no enable keep the flips flops at the same value %
count[].d = count[].q;
END IF;
rco = ((count[].q == 9) & ent);% generate the rco when the count is nine and ent is true %
END;
In the dec_count subdesign a 4 bit counter is defined. There are four inputs consisting of
the clock, two enables (ent & enc) and a clear. The outputs are the four count bits and a
Ripple Carry out (rco). In the variable section 4 D type flip-flops are declared local to the
subdesign. The comments in the file explain the operation.
Create a new project called YI_dec_counter within a new folder called YI_dec_counter
under your main folder. Create your project from a new bdf file and name it
YI_dec_counter.
Enter this design in a new AHDL file called YI_dec_count.tdf and “Create Symbol File” to
allow you to enter the symbol into the bdf file (Figure 46). Make sure to label all the wires
as in Figure 46.
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Figure 46. Decade Counter Block
Now compile and simulate the design and print out the resulting simulation file. For creating
the clock waveform first of all highlight it by left-clicking on the clock. Then click on the
Overwrite Clock button. In the dialog box (Figure 47) set the period and duty cycle of the
clock.
Figure 47. Clock Dialog
Figure 48 shows the simulation input waveform.
Figure 48. Simulation input waveform
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Before you simulate you should choose Simulation ? Options (as before) and ensure that
the Quartus II Simulator radio button is selected. Choose a functional simulation, to avoid
the slightly approximate timings mentioned in the Supporting information. Your simulation file
name should include your initials as always, in the form YI_DecCounter.vwf and as always
this should be readable from the title of the window (Figure 49).
This is only one example of the simulation input signals. Your simulation file does not
necessarily need to be like this. For your report, you should choose a different clock period
and a different combination of values for the other three control signals. In your report you
should explain what happens at each period of time. For example when enc is 0 the output
is not changed even though there are two rising edges of the clock in this period.
Figure 49. Simulation output file
As you have constructed a 7-segment decoder, connect the dec_count module to the input
of the 7-segment decoder (Figure 50). [How? One way is to copy the YI_dec_count.tdf file
to the _7SegmentDecoder project folder, then open it within that project folder, then select
File ? Create / Update ? Create Symbol Files for Current File. Then insert the dec_count
module to the YI_7SegmentDecoder.bdf schematic.] Check carefully that your resultant
schematic design matches Figure 50.
Figure 50. Design with Decade Counter
Your decade counter is now providing inputs to your 7-segment decoder. The inputs are the
binary numbers equivalent to 0-9, which you previously (Section 2.5) would have had to
provide manually – and inefficiently – by flipping four of the toggle switches on the DE1
board in the appropriate combinations (see also ‘Supporting material’ Sections 2.2 and 3.1).
The toggle switches now perform the functions associated with ent, enc and clear instead.
Your updated design is now ready for programming the Cyclone II FPGA again. Perform a
functional simulation of your design using the method already outlined. Remember that the
clock input is on pin L1 which is a 50 MHz clock. Choose a 50 MHz clock, but as above, you
should choose your own combinations of values for the other three control signals.
Exp 28 Part II, Ver. 7, Apr 2020
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3.2. Modified counter [18 Marks]
If you tried this design on the FPGA you would find that all the segments of the display
appear permanently on. This is what you would expect with a clock frequency of 50 MHz! If
we want the counter to increment approximately every second, we will need to enable the
counter for a single clock period after every 50 million clock pulses. We can construct
another counter to do this and then use the output to drive one of the enables. (Don’t use the
output of the counter to drive the clock as this would make the design “Asynchronous”).
SUBDESIGN sec_cnt
(
clk : INPUT;
second : OUTPUT;
)
VARIABLE
count[25..0] : DFF;
BEGIN
count[].clk = clk;
IF ((count[].q == 50000000)) THEN
count[].d = 0;
second = VCC;
ELSE
count[].d = count[].q + 1;
second = GND;
END IF;
END;
Create a TDF file called YI_sec_cnt.tdf and enter the code to produce a pulse every
second. Then integrate this with the previous design to produce a circuit which counts every
second (Figure 51).
Figure 51. Modified design counting once per second
If you now programmed the FPGA, you would be able to see that the rightmost 7-segment
display increments every second, and you could test the Clear and Enable switches.
1) If you try and simulate the design you will find that a useful simulation period would
be far beyond the maximum ‘End Time’ available (100 us). Even if a longer
simulation window was available, a useful simulation would take a very long time as
Exp 28 Part II, Ver. 7, Apr 2020
30
the counter would have to count to 50000000 before incrementing the dec_count.
Standard practice is to modify the count value for simulation purposes, i.e. change
the count value from 50000000 to a more manageable value like 5. Do this and
simulate the new design.
2) You may have noticed by now that a simulated clock period of 50 ns does not
actually simulate a 50MHz clock. Work out the clock period of a 50MHz clock (or find
another way to directly simulate a 50MHz clock in the Simulation Waveform Editor),
and re-simulate your design. Calculate the expected time between increments (using
your modified count value from above) and check that this matches your simulation.
Include this in your discussion.
3) Technically speaking, the modification you have carried out by means of the above
TDF file contains a tiny error which would cause the counter to increment very
slightly less than once a second. Eventually (after more than a year and a half), even
if it worked perfectly your counter would lag a whole second behind a counter which
truly increments exactly once per second. What simple correction could be made to
the TDF file so that the counter should now increment exactly once per second?
4) Modify your design to make it a divide-by-12 counter (mod-12 counter – i.e. a counter
which counts to 12), designed to display the results in hexadecimal as 0 to B on a
single 7-segment display. Record your simulation results (screenshots).
5) Now try cascading two divide-by-12 counters together and display the resulting
values on two segments of the quad 7-segment display (It will count up every 1
second). Record some results (screenshots) showing that the counter counts from 00
up to BBH.
Figure 52 is a sample simulation for the modified dec_count. Simulate your counter
differently and explain the effect of the control inputs.
Figure 52. Simulation waveform
Counter is
disabled
Counter is
reset
Counter is
incremented
Exp 28 Part II, Ver. 7, Apr 2020
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4. Design Assignments [30 Marks]
Now that you are familiar with the state machine entry (see Prelab material), design and
simulate digital circuits with the following specifications. Begin all filenames with “YB_”:
4.1. Single Pulsar [10 Marks]
Generate a single pulsar state machine i.e. a machine which produces an output for 1 clock
period when one of the push buttons is pressed. Use either KEY0 or KEY1 as the
pushbutton in your design. To decide, convert the final digit of your student number into
binary. If the result ends in “0”, use KEY0. If it ends in “1”, use KEY1. Include also a
synchronous reset input as shown in the Prelab examples. Simulate your design with a
timing simulation. Simulate a 50Hz clock frequency, and disable the ‘Snap to Grid’ option.
In your design you need to consider these problems:
1) Generating a single pulse
2) Pulse synchronization
The first problem is the pulse duration. The pushbutton (input) pulse is usually much longer
(millisecond range) than one clock period (microseconds or nanoseconds) – however, we
require that this would still generate only a single output pulse (for one clock period). On the
other hand, if the input pulse is less than one clock period, no pulse should be generated.
Your design must consider these points and you need to verify them by simulation.
The second problem concerns the setup and hold times for the flip-flops to which the input is
connected. Most modern flip-flop hold times are negligible (zero or even negative!) but setup
times are significant. If the input is synchronised with the falling edge of the clock then it will
satisfy the setup and hold times of a positive edge triggered finite state machine. On the
board, the input start time would depend on precisely when the pushbutton is pressed. In
your annotated timing simulation, you should show that the minimum required input pulse
length when the input starts exactly at the falling clock edge, does not produce output if the
same length pulse starts exactly on the rising clock edge. (Note: if the hint below is followed
as intended, you will find in simulations that your minimum required input pulse length is not
as short as one clock period.) Can you go further and use your simulations to estimate the
setup time of the simulated flip-flops?
Design and simulate an ASM for the single pulsar to satisfy the above requirements using
the AHDL design entry method (.tdf) including a ‘Table’. The following state diagram is a hint
(it is incomplete in the sense that it does not show you the output and input values
associated with the states and transitions.) Your design must ignore input pulses with
duration of less than one clock cycle, and output should be produced for only 1 clock
period even when the input pulse is much longer than this. You can design this finite
state machine as a Mealy or Moore machine. However, in general the timing is less critical in
a Moore machine than in a Mealy machine, and so it is suggested to use a Moore machine.
Figure 53.
Your report must include a description of your design, an ASM chart or state diagram
(including inputs/outputs), and annotated simulations to cover all the possible timings.
Exp 28 Part II, Ver. 7, Apr 2020
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4.2. Pushbutton Enabled Counter [10 Marks]
Modify your Decade Counter schematic design so that the output of the single pulsar is used
to enable the counter, such that it increments by one when the pushbutton is pressed (KEY0
or KEY1 is connected to the input of the single pulsar circuit). Your schematic should include
pin assignments so that the design is ready to be programmed to the DE1 board. (See
Supporting material Section 2.3 for information relevant to the input pin assignments in this
case. Don’t forget that your pin assignment for the input pulse should match the pushbutton
you chose in the previous section. Assign one of the toggle switches to the reset input.) Test
your design with simulations.
Your report must include the schematic diagram and annotated simulations.
4.3. Adder/Subtractor Logic Design [10 Marks]
Design a logic circuit using the AHDL or schematic entry method to add or subtract two
signed 4-bit numbers. The most significant bit of each number is the sign bit; therefore the
range of input numbers would be -8 to +7. The result would be a signed 4-bit number too.
A control input, Add/Sub, will determine the addition or subtraction operation. If the result is
out of the range then an overflow flag must be set. For example the addition of 4 and 5 or
the subtraction of -3 and 7 should set the overflow flag.
The circuit must be fully synchronous, which means all the inputs and outputs must be
registered by a master clock.
The circuit should have a master reset connected to all of the registers and flip-flops.
In adding signed numbers the overflow can be detected by XORing the two inputs’ sign bits
with the result’s sign bit and carry_out bit (A 4-input XOR is needed). You can detect the
overflow with other methods.
If you use the schematic design entry you can insert the 7483 (4-bit Full-Adder) and 74171
(quad-DFF) symbols in your design from the library.
The Adder circuit can be used for subtraction if you use the two’s complement of the
subtracted number.
Simulate your design to prove that it works with all possible combinations of inputs. Include
combinations of positive and negative inputs with the addition or subtraction operations, to
generate or not to generate overflows.
Your schematic should include pin assignments, planned for implementation of your design
on Altera’s Cyclone II FPGA board using the Toggle switches and seven segments. Use the
left-hand seven-segment to display the sign and the right-hand seven-segment for the
absolute value of the number.
You will need to convert the signed result to an absolute value and use a flip-flop for the sign
signal.
Your report must include the schematic diagram and annotated simulations.
Please continue to the next page for Section 5 (‘Assessment and Marking Scheme’)
and Section 6 (‘Plagiarism and Collusion’).
There is an opportunity to provide your feedback on the page afterwards – copy and
paste this into your report if you would like.
Exp 28 Part II, Ver. 7, Apr 2020
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5. Assessment and Marking Scheme
This experiment is assessed by means of a pre-lab test and practical design /
simulation work.
The marking scheme for this workbook is as follows:
? The pre-lab test: 30 Marks
? The practical work: 70 Marks (use submission template available on VITAL)
6. Plagiarism and Collusion
Plagiarism and collusion or fabrication of data is always treated seriously, and action
appropriate to the circumstances is always taken. The procedure followed by the
University in all cases where plagiarism, collusion or fabrication is suspected is
detailed in the University’s Policy for Dealing with Plagiarism, Collusion and
Fabrication of Data, Code of Practice on Assessment, Category C, available on
http://www.liv.ac.uk/tqsd/pol_strat_cop/cop_assess/appendix_L_cop_assess.pdf.
Follow the following guidelines to avoid any problems:
(1) Do your work yourself.
(2) Acknowledge all your sources.
(3) Present your results as they are.
(4) Restrict access to your work.
Version history
Name Date Version
Dr D G McIntosh April 2020 Ver. 7
Dr D G McIntosh March 2020 Ver. 6.5
Dr M López-Benítez September 2019 Ver. 6.4
Dr M López-Benítez December 2017 Ver. 6.3
Dr L Esteban and Dr M López-Benítez November 2017 Ver. 6.2
Dr A Al-Ataby October 2014 Ver. 6.1
Dr A Al-Ataby, F Davoodi Samirmi and Prof J Smith October 2013 Ver. 6
Dr A Al-Ataby October 2012 Ver. 5.8
Prof J S Smith October 2011 Ver. 5.7
Dr S Amin-Nejad July 2011 Ver. 5.6
Exp 28 Part II, Ver. 7, Apr 2020
34
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