CSSE2010/7201辅导、C++,Java语言程序

日期：2022-09-09 07:34

- Introduction to Computer Systems
Assignment 1: Digital Logic Design
Semester 2, 2022
Due: Friday, 09 September 2022, 4:00PM AEST via Blackboard submission
This assignment is worth 20% of your grade. Revision 1.0
This assignment involves a design task and a circuit construction (for internal mode)/simulation (for external
mode) task as outlined below.
? Design task (Part A): Provide design details for the problem specification given in Part A. For both
internal and external students, submission for this part is a PDF document, either electronically typeset
or handwritten and scanned. No simulation or circuit construction is required for this part.
Circuit Construction/Simulation task (Part B): Verify the functionality of the given circuit de-
scribed in Part B via circuit construction (internal mode students) or Logisim simulation (external mode
students). Submission for this part include:
– Internal mode: A photo of the constructed circuit and a video showing the operation of the circuit.
– External mode: Logisim/Logisim evolution file and a screen recording showing the simulation.
Submission is a single .zip file containing the above and more details are given in the submission section of
this document.
Part A - Design Task [12 Marks]
Consider the 3-input Boolean function F = f(A,B,C) defined based on the last digit of your 8-digit student
number as shown in Table 1. Here, A,B,C are single bit binary variables.
Table 1: Definition of the given Boolean function F = f(A,B,C) based on the last digit of the 8-digit student number.
Here, “+” indicates arithmetic addition. When listed in a truth table, you should have the input variable A as the MSB
(left most input column) and C the LSB (right most input column). The table only specifies conditions for F = 1 and
it is implied that F = 0 otherwise.
Last digit of 8-digit
student number
Definition of the function
F = f(A,B,C)
0-1 F = 1 if C ≥ (A+B)
2-3 F = 1 if (A+B + C) > 0 and the unsigned number ABC is exactly divisible by 3 or 5 or 7
4-5 F = 1 if (A+B + C) > 0 and the unsigned number ABC is exactly divisible by 2 or 7
6-7 F = 1 if C < (A+B)
8-9 F = 1 if a majority of inputs are 0
Select the definition for F from the table above based on the last digit of your student number and complete
the following steps:
1. Provide a truth table for the function F = f(A,B,C) [2 marks].
2. Provide (un-simplified) sum-of-product (SOP) Boolean expression for F [2 marks].
3. Provide a simplified SOP expression for F containing only two variables in each product term [2 marks].
4. Provide a logic diagram for F based on the simplified SOP expression in step 3 using AND/OR/NOT
gates [2 marks].
5. Provide a circuit schematic diagram for a 2-input NAND only implementation of F [2 marks].
6. Using a logic diagram, show how F can be implemented only using a 4:1 multiplexer and NOT
gates [2 marks].
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Part B - Circuit Construction/Simulation Task [8 Marks]
This task requires you to verify the functionality of a given digital circuit by constructing and testing the circuit
on a breadboard (for internal mode students) or by simulating in Logisim (for external mode students).
The circuit to be tested is called a “4-bit binary counter with configurable output detection,” as shown in Fig. 1
and explained below. The circuit contains a 4-bit binary counter (shown in Fig. 2) which outputs a count value
0 ≤ CNT ≤ 15 when clock pulses are provided by a push button. When the count value reaches a particular
number X, an output LED is to be turned ON, where the number X is provided by the user using 4 switches.
i.e. when CNT = X an LED should be turned ON and the value 0 ≤ X ≤ 15 is user-configurable via switches.
The given circuit in Fig. 1 achieves this functionality by taking the 4-bit counter output CNT ≡ Q3Q2Q1Q0,
performing the subtraction (X ?CNT ) using a 4-bit adder and detecting whether the result of (X ?CNT ) is
zero using some combinational logic. Note that, the circuit performs (X?CNT ) rather than (CNT?X) because
it is easier to obtain the two’s complement of CNT for subtraction by using the Q values directly available from
flip-flops. That is, the 4-bit adder performs the operation (X ? CNT ) = (X + (?CNT )) = (X + CNT + 1),
where (CNT + 1) is the two’s complement of CNT . Therefore, the adder takes Q outputs from the counter
and sets the carry-in at LSB to 1, thus performing (X + CNT + 1).
The main circuit is shown in Fig. 1 and the 4-bit counter is also shown in Fig. 2. Note that the 4-bit counter
used in this problem is known as an “asynchronous counter” because the four flip-flops do not share a common
clock. The main operational clock signal (i.e. the clock signal for flip-flop 0) is provided by the user using push
button presses. The counter counts up when the user presses the push button.
Figure 1: Four bit counter with configurable output detection.
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Q0
D0 Q0
Q1
D1 Q1
Q2
D2 Q2
Q3
D3 Q3
CLK
Q0 Q1 Q2 Q3
Figure 2: Four bit asynchronous binary counter circuit.
Your task is to verify the operation of this circuit shown in Fig. 1.
Internal mode students: Construct the circuit on breadboard using the logic chips and IO board and verify
the correct operation. Submission includes a photo of your constructed circuit and a video showing the
functionality.
External mode students: Create the circuit in Logisim and verify the correct operation via simulation.
Submission includes your Logisim/Logisim Evolution file and a screen recording of your simulation.
Test Cases
To demonstrate the functionality of the circuit, your video (or the screen recording for external students) must
show two test cases corresponding to when the value of X is equal to the last two digits of your student
number. If the last two digits of your student number are the same, then the second test case should use the
next digit in the student number which is not equal to the last two digits.
Example: If your 8-digit student number is 12345678 you should perform two tests when X = 7 (0111 in binary)
and X = 8 (1000 in binary). You must reset the circuit before each test by turning the I/O board off and on
again. Counting is performed by pressing the push button. On the first test for X = 7 (second last digit of your
student number), you must set the switches to S3S2S1S0 = 0111, observe the output LED is OFF, and count
up to 7 and show that the output LED turns ON when counter reaches X = 7. On the second test, for X = 8
(last digit of your student number), you must set the switches to S3S2S1S0 = 1000, observe the output LED
is OFF, and count up to X = 8 and show the LED turning ON, and further count up beyond 15, wrapping
back to 0, and count up to X = 8 again, showing the LED turning ON again. If your 8-digit student number
contains equal last 2 digits such as 12345677, then your two test cases should use X = 7 and X = 6.
External mode students should use Logisim input switches/buttons and output LEDs accordingly and optionally
use a RESET input to flip-flops to reset the counter back to 0000, between the two test cases.
Steps to Build the Circuit
To minimise errors in building and testing the circuit, it is highly recommended that you build the circuit
progressively as detailed below, and test the circuit behaviour at each stage. Your are only required to submit
a final video showing the operation of the circuit as outlined above. However, you may want to record the
output of each incremental step below, so that, if your final circuit doesn’t work, you can submit the outputs
of progressive steps and receive partial marks for any correct intermediate outputs. If your final circuit is
fully working, then there is no need to submit the intermediate recordings. Marks will be awarded based on
demonstrated functionality only. Internal mode students will need at least 5 logic ICs to build the complete
circuit and additional wire kits can be provided during the lab sessions, if needed.
1. Start with the two least significant bits of the 4-bit binary counter. This should be implemented with a
74HCT74 (Dual D-Type Flip-flop), as you will need access to each flip-flop’s clock input. Start with the
first flip-flop, connecting the CLK input to a button on the I/O board. Connect Q to the D input, and
make sure you connect the CLR and SET inputs appropriately. You should notice the output Q toggle
on each button press. Repeat this for the second flip-flop on the same chip, with the CLK input coming
from the previous flip-flop’s Q output. Connect the Q outputs of both flip-flops to two LEDs to ensure
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that this is a 2-bit binary counter. External mode students should use D flip-flops in Logisim. Take a
quick recording. [1 mark]
2. Add another 74HCT74 (Dual D-Type Flip-flop) next to the previous one. Construct and test it as detailed
above. Once verified, connect the first chip’s most significant Q to the CLK of the second chip’s least
significant flip-flop. The result should be four cascaded D flip-flops, arranged to form a 4-bit binary
counter (see Fig. 2). Connect the Q output of each flip-flop to an LED, and verify its behaviour. Using
the button connected in the previous step, you should be able to count up from 0000 in binary to 1111,
and then wrap back to 0000. External mode students should use D flip-flops in Logisim. Take a quick
recording of this step. [2 marks]
3. Add a 74HCT283 (4-bit full adder) chip to your circuit as the third chip. Connect one set of inputs to
switches S0 ? S3 on the I/O board. Connect the other set of inputs of the adder to the Q outputs of the
4-bit counter constructed earlier. You should also connect the carry-in (at LSB) input of the adder to
logic 1. Connect the 4 outputs of the adder to 4 LEDs and verify the correct operation of the circuit. On
each button press, copy the count value (shown on the LEDs) to the switch inputs, and verify that the
adder output is zero. External mode students should use the adder block available in Logisim and set the
data width to 4 bits. Take a quick recording of this step. [3 marks]
4. Finally, add the combinational output logic, using any chips you prefer, to implement a 4-input NOR gate.
At this stage, you can remove the adder outputs connecting to 4 LEDs in step 3. The final output LED
should be ON, only when the count value matches with the number X represented by the 4 switches. You
can then perform the two test cases mentioned above as per your student number and take a recording.
If all the above steps are successful, you only need to submit this final recording demonstrating the two
test cases. [2 marks]
Submission Process
Your submission should include a zipped folder (a .zip file only, not any other format such as .rar or .7z)
containing your response as follows.
For internal mode students, please submit a zip file containing:
A .pdf file containing your solution for Part A and your name and student number. This can be either
electronically typeset or handwritten and scanned.
A picture of your circuit for Part B including your student ID card, clearly showing your student number
(.png or .jpg/.jpeg only) and circuit.
A video (not more than 5 minutes long) showing the required functionality of your circuit for Part B.
For external mode students, please submit a zip file containing:
A .pdf file containing your solution for Part A and your name and student number. This can be either
electronically typeset or handwritten and scanned.
Your logisim .circ file for Part B.
A screen recording (not more than 5 minutes long) showing the required functionality of your circuit for
Part B. You can do the screen recording via Zoom.
This single zip file you submit must be named as A1 xxxxxxxx.zip, where xxxxxxxx is your 8-digit student
number, and should be submitted electronically to Blackboard according to the exact instructions listed on the
Blackboard website.
You can submit your assignment multiple times before the deadline but only the last submission before the
deadline will be marked. Only submit the zip file as described above. You are responsible for ensuring that you
have submitted the files that you intended to submit, you are encouraged to download your submission from
Blackboard and ensure it contains the correct files.
Submitted work should be neat, legible and simple to understand - you may be penalised for work that is untidy
or difficult to read.
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While you can collaborate to clarify any doubts in the learning material required for the assignment, the work
you submit must be your own and this are an individual assignment. If any signs of plagiarism/collusion
is detected or there are any doubts about the origin of your submission you may be requested to attend a
subsequent oral assessment as decided by the course coordinator. Failure to attend such an oral assessment or
failure to satisfactorily answer questions about your submission will result in zero marks for the assignment.
Late Penalties: Where an assessment item is submitted after the deadline, without an approved extension, a
late penalty will apply. The late penalty shall be 10% of the maximum possible mark for the assessment item
will be deducted per calendar day (or part thereof), up to a maximum of seven (7) days. After seven days, no
marks will be awarded for the item. A day is considered to be a 24 hour block from the assessment item due
time. Negative marks will not be awarded.
Criteria
This assignment will be marked out of 20 and is worth 20% of your overall grade.
Part A - 12 marks
Truth Table - 2 marks
2: Fully correct truth table.
1: Somewhat correct truth table with one error.
0: Incorrect truth table.
Sum-of-product Boolean Expression - 2 marks
Marked relative to the given truth table, unless there are major omissions.
2: Fully correct expression.
1: Mostly correct expression, with one error.
0: No logic expression or incorrect logic expression.
Simplified Sum-of-product Boolean Expression - 2 marks
Simplification of SOP expression from previous step. Must contain only two variables in each product term.
2: Fully correct expression.
1: Mostly correct expression with one error, or simplifies to more than two variables in each term.
0: No logic expression or incorrect logic expression.
Logic Diagram - 2 marks
Derived from the simplified Boolean expressions.
2: Fully correct logic diagram.
1: Mostly correct logic diagram, with a few errors or omissions.
0: Missing logic diagram or a diagram containing major errors.
Circuit Schematic - 2 marks
NAND-only implementation. Schematic must follow the “Guide to Circuit Schematics” from Blackboard.
2: Fully correct circuit schematic.
1: Mostly correct circuit schematic, with a few errors or omissions.
0: Missing circuit schematic, a schematic containing major errors, or a schematic that does not use only
NAND gates.
5
Multiplexer implementation - 2 marks
This can be a logic diagram. Implementation must use only a 4:1 multiplexer and NOT gates.
2: Fully correct implementation.
1: Mostly correct implementation, with minor errors.
0: No implementation, an implementation that does not use a multiplexer, or an implementation containing
major errors.
Part B - 8 marks
Full marks will be awarded to a fully correct solution. Part marks will be awarded for implementation of
each module individually. Marks are awarded based on the demonstrated functionality only. No marks will be
awarded for attempting the circuit construction/simulation.
Binary Counter - 3 marks
3: Fully correct 4-bit counter circuit functionality.
2: Mostly correct binary counter implemented, with minor functionality errors.
1: Some evidence of a binary counter implemented, with multiple errors.
0: No implementation of binary counter.
Adder - 3 marks
3: Fully correct 4-bit adder performing the required subtraction correctly.
2: Mostly correct adder implemented, with minor errors.
1: Some evidence of an adder implemented, with multiple errors, or circuit adding instead of subtracting.
0: No implementation of adder implementation.
Combinational Logic - 2 marks
2: Fully correct output logic.
1: Partially correct output logic, or implementation requiring more than two 74-series chips.
0: No implementation of output logic.
Overall functionality
Full marks are awarded if two test cases are demonstrated successfully.
Total mark is capped at 6 if only one test case is demonstrated successfully.
Total mark is capped at 5 if only the individual components are demonstrated but no test cases based on
the student number are provided as required.